Marvell’s 2nm IP Platform Enables Custom Silicon for Datacenters

Marvell this week introduced its new IP technology platform specifically tailored for custom chips for accelerated infrastructure made on TSMC’s 2nm-class process technologies (possibly including N2 and N2P). The platform includes technologies essential for developing cloud-optimized accelerators, Ethernet switches, and digital signal processors.

The 2nm platform will enable Marvell to deliver highly differentiated analog, mixed-signal, and foundational IP to build accelerated infrastructure,” said Sandeep Bharathi, chief development officer at Marvell. “Our partnership with TSMC on our 5nm, 3nm and now 2nm platforms has been instrumental in helping Marvell expand the boundaries of what can be achieved in silicon.

The 2nm platform is built on Marvell’s extensive IP portfolio, which includes advanced SerDes capable of speeds beyond 200 Gbps, processor subsystems, encryption engines, SoC fabrics, and high-bandwidth physical layer interfaces. These IPs are crucial for developing and producing a range of devices, such as custom compute accelerators and optical interconnect digital signal processors. These are becoming common building blocks for AI clusters, cloud data centers, and other infrastructures supporting machines used for AI and HPC workloads.

While these IPs are vital for a variety of processors, DSPs, and networking gear, developing them from scratch—especially for TSMC’s 2nm-class process technologies that rely on gate-all-around Nanosheet transistors—is hard, time-consuming, and sometimes inefficient, both from a die space and economics point of view. This is where Marvell’s IP portfolio promises to be very useful.

Marvell does not outright say that its TSMC 2nm-certified platform is silicon-proven, but given the fact that TSMC has been working with IP providers over N2-compatible IPs for quite some time, it is reasonable to expect that at least some of Marvell’s popular IPs are.

We take a modular approach to semiconductor design R&D, focusing first on qualifying foundational analog, mixed-signal IP and advanced packaging that can be used across a broad spectrum of devices,” Bharathi said. “This allows us to bring innovations such as process manufacturing advances faster to market.

Meanwhile, Marvell is not part of TSMC’s Open Innovation Platform and OIP’s IP Alliance, so it is unclear whether the company’s N2-compatible IPs will be part of TSMC’s TSMC9000 IP program, which greatly simplifies IP choices for chip designers.

TSMC is pleased to collaborate with Marvell in pioneering a platform for advancing accelerated infrastructure on our 2nm process technology,” said Kevin Zhang, senior vice president of business development at TSMC. “We are looking forward to our continued collaboration with Marvell in the development of leading-edge connectivity and compute products utilizing TSMC’s best-in-class process and packaging technologies.

Source: Marvell

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